Payment Terms | T/T |
Supply Ability | By case |
Delivery Time | 2-4 weeks |
Packaging Details | custom cartons |
Crystal Structure | 4H-SiC, 6H-SiC |
Resistivity | Conductive Type: 0.01 - 100 Ω·cm;Semi-Insulating Type (HPSI): ≥ 10⁹ Ω·cm |
Thermal Conductivity | ~490 W/m·K |
Surface Roughness | Ra < 0.5 nm |
Bandgap | ~3.2 eV (for 4H-SiC) |
Breakdown Electric Field | ~2.8 MV/cm (for 4H-SiC) |
Brand Name | ZMSH |
Place of Origin | China |
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Product Specification
Payment Terms | T/T | Supply Ability | By case |
Delivery Time | 2-4 weeks | Packaging Details | custom cartons |
Crystal Structure | 4H-SiC, 6H-SiC | Resistivity | Conductive Type: 0.01 - 100 Ω·cm;Semi-Insulating Type (HPSI): ≥ 10⁹ Ω·cm |
Thermal Conductivity | ~490 W/m·K | Surface Roughness | Ra < 0.5 nm |
Bandgap | ~3.2 eV (for 4H-SiC) | Breakdown Electric Field | ~2.8 MV/cm (for 4H-SiC) |
Brand Name | ZMSH | Place of Origin | China |
SiC Substrate & Epi-wafer Product Portfolio Brief
We offer a comprehensive portfolio of high-quality silicon carbide (SiC) substrates and wafers, covering multiple polytypes and doping types (including 4H-N type [N-type conductive], 4H-P type [P-type conductive], 4H-HPSI type [High-Purity Semi-Insulating], and 6H-P type [P-type conductive]), with diameters ranging from 4-inch, 6-inch, 8-inch up to 12-inch. In addition to bare substrates, we provide high-value-added epitaxial wafer growth services, enabling precise control over epi-layer thickness (1–20 µm), doping concentration, and defect density.
Each SiC substrate and epitaxial wafer undergoes rigorous in-line inspection (e.g., micropipe density <0.1 cm⁻², surface roughness Ra <0.2 nm) and comprehensive electrical characterization (such as CV testing, resistivity mapping) to ensure exceptional crystal uniformity and performance. Whether used for power electronics modules, high-frequency RF amplifiers, or optoelectronic devices (e.g., LEDs, photodetectors), our SiC substrate and epitaxial wafer product lines meet the most demanding application requirements for reliability, thermal stability, and breakdown strength.
The 4H-N type silicon carbide substrate maintains stable electrical performance and thermal robustness under high-temperature and high-electric-field conditions, owing to its wide bandgap (~3.26 eV) and high thermal conductivity (~370-490 W/m·K).
Core Characteristics:
N-Type Doping: Precisely controlled nitrogen doping yields carrier concentrations ranging from 1×10¹⁶ to 1×10¹⁹ cm⁻³ and room-temperature electron mobilities up to approximately 900 cm²/V·s, which helps minimize conduction losses.
Low Defect Density: The micropipe density is typically < 0.1 cm⁻², and the basal-plane dislocation density is < 500 cm⁻², providing a foundation for high device yield and superior crystal integrity.
Excellent Uniformity: The resistivity range is 0.01–10 Ω·cm, substrate thickness is 350–650 µm, with doping and thickness tolerances controllable within ±5%.
6inch 4H-N type SiC wafer's specification | ||
Property | Zero MPD Production Grade (Z Grade) | Dummy Grade (D Grade) |
Grade | Zero MPD Production Grade (Z Grade) | Dummy Grade (D Grade) |
Diameter | 149.5 mm - 150.0 mm | 149.5 mm - 150.0 mm |
Poly-type | 4H | 4H |
Thickness | 350 µm ± 15 µm | 350 µm ± 25 µm |
Wafer Orientation | Off axis: 4.0° toward <1120> ± 0.5° | Off axis: 4.0° toward <1120> ± 0.5° |
Micropipe Density | ≤ 0.2 cm² | ≤ 15 cm² |
Resistivity | 0.015 - 0.024 Ω·cm | 0.015 - 0.028 Ω·cm |
Primary Flat Orientation | [10-10] ± 50° | [10-10] ± 50° |
Primary Flat Length | 475 mm ± 2.0 mm | 475 mm ± 2.0 mm |
Edge Exclusion | 3 mm | 3 mm |
LTV/TIV / Bow / Warp | ≤ 2.5 µm / ≤ 6 µm / ≤ 25 µm / ≤ 35 µm | ≤ 5 µm / ≤ 15 µm / ≤ 40 µm / ≤ 60 µm |
Roughness | Polish Ra ≤ 1 nm | Polish Ra ≤ 1 nm |
CMP Ra | ≤ 0.2 nm | ≤ 0.5 nm |
Edge Cracks By High Intensity Light | Cumulative length ≤ 20 mm single length ≤ 2 mm | Cumulative length ≤ 20 mm single length ≤ 2 mm |
Hex Plates By High Intensity Light | Cumulative area ≤ 0.05% | Cumulative area ≤ 0.1% |
Polytype Areas By High Intensity Light | Cumulative area ≤ 0.05% | Cumulative area ≤ 3% |
Visual Carbon Inclusions | Cumulative area ≤ 0.05% | Cumulative area ≤ 5% |
Silicon Surface Scratches By High Intensity Light | Cumulative length ≤ 1 wafer diameter | |
Edge Chips By High Intensity Light | None permitted ≥ 0.2 mm width and depth | 7 allowed, ≤ 1 mm each |
Threading Screw Dislocation | < 500 cm³ | < 500 cm³ |
Silicon Surface Contamination By High Intensity Light | ||
Packaging | Multi-wafer Cassette Or Single Wafer Container | Multi-wafer Cassette Or Single Wafer Container |
8inch 4H-N type SiC wafer's specification | ||
Property | Zero MPD Production Grade (Z Grade) | Dummy Grade (D Grade) |
Grade | Zero MPD Production Grade (Z Grade) | Dummy Grade (D Grade) |
Diameter | 199.5 mm - 200.0 mm | 199.5 mm - 200.0 mm |
Poly-type | 4H | 4H |
Thickness | 500 µm ± 25 µm | 500 µm ± 25 µm |
Wafer Orientation | 4.0° toward <110> ± 0.5° | 4.0° toward <110> ± 0.5° |
Micropipe Density | ≤ 0.2 cm² | ≤ 5 cm² |
Resistivity | 0.015 - 0.025 Ω·cm | 0.015 - 0.028 Ω·cm |
Noble Orientation | ||
Edge Exclusion | 3 mm | 3 mm |
LTV/TIV / Bow / Warp | ≤ 5 µm / ≤ 15 µm / ≤ 35 µm / 70 µm | ≤ 5 µm / ≤ 15 µm / ≤ 35 µm / 100 µm |
Roughness | Polish Ra ≤ 1 nm | Polish Ra ≤ 1 nm |
CMP Ra | ≤ 0.2 nm | ≤ 0.5 nm |
Edge Cracks By High Intensity Light | Cumulative length ≤ 20 mm single length ≤ 2 mm | Cumulative length ≤ 20 mm single length ≤ 2 mm |
Hex Plates By High Intensity Light | Cumulative area ≤ 0.05% | Cumulative area ≤ 0.1% |
Polytype Areas By High Intensity Light | Cumulative area ≤ 0.05% | Cumulative area ≤ 3% |
Visual Carbon Inclusions | Cumulative area ≤ 0.05% | Cumulative area ≤ 5% |
Silicon Surface Scratches By High Intensity Light | Cumulative length ≤ 1 wafer diameter | |
Edge Chips By High Intensity Light | None permitted ≥ 0.2 mm width and depth | 7 allowed, ≤ 1 mm each |
Threading Screw Dislocation | < 500 cm³ | < 500 cm³ |
Silicon Surface Contamination By High Intensity Light | ||
Packaging | Multi-wafer Cassette Or Single Wafer Container | Multi-wafer Cassette Or Single Wafer Container |
Target Applications:
Primarily used for power electronic devices such as SiC MOSFETs, Schottky diodes, and power modules, widely applied in electric vehicle drivetrains, solar inverters, industrial drives, and traction systems. Its properties also make it suitable for high-frequency RF devices in 5G base stations.
The 4H Semi-Insulating SiC substrate possesses extremely high resistivity (typically ≥ 10⁹ Ω·cm), which effectively suppresses parasitic conduction during high-frequency signal transmission, making it an ideal choice for manufacturing high-performance radio frequency (RF) and microwave devices.
Core Characteristics:
6Inch 4H-semi SiC substrate specification | ||
Property | Zero MPD Production Grade (Z Grade) | Dummy Grade (D Grade) |
Diameter (mm) | 145 mm - 150 mm | 145 mm - 150 mm |
Poly-type | 4H | 4H |
Thickness (um) | 500 ± 15 | 500 ± 25 |
Wafer Orientation | On axis: ±0.0001° | On axis: ±0.05° |
Micropipe Density | ≤ 15 cm-2 | ≤ 15 cm-2 |
Resistivity (Ωcm) | ≥ 10E3 | ≥ 10E3 |
Primary Flat Orientation | (0-10)° ± 5.0° | (10-10)° ± 5.0° |
Primary Flat Length | Notch | Notch |
Edge Exclusion (mm) | ≤ 2.5 µm / ≤ 15 µm | ≤ 5.5 µm / ≤ 35 µm |
LTV / Bowl / Warp | ≤ 3 µm | ≤ 3 µm |
Roughness | Polish Ra ≤ 1.5 µm | Polish Ra ≤ 1.5 µm |
Edge Chips By High Intensity Light | ≤ 20 µm | ≤ 60 µm |
Heat Plates By High Intensity Light | Cumulative ≤ 0.05% | Cumulative ≤ 3% |
Polytype Areas By High Intensity Light | Visual Carbon Inclusions ≤ 0.05% | Cumulative ≤ 3% |
Silicon Surface Scratches By High Intensity Light | ≤ 0.05% | Cumulative ≤ 4% |
Edge Chips By High Intensity Light (Size) | Not Permitted > 02 mm Width and Depth | Not Permitted > 02 mm Width and Depth |
The Aiding Screw Dilation | ≤ 500 µm | ≤ 500 µm |
Silicon Surface Contamination By High Intensity Light | ≤ 1 x 10^5 | ≤ 1 x 10^5 |
Packaging | Multi-wafer Cassette or Single Wafer Container | Multi-wafer Cassette or Single Wafer Container |
4-Inch 4H-Semi Insulating SiC Substrate Specification | ||
---|---|---|
Parameter | Zero MPD Production Grade (Z Grade) | Dummy Grade (D Grade) |
Physical Properties | ||
Diameter | 99.5 mm – 100.0 mm | 99.5 mm – 100.0 mm |
Poly-type | 4H | 4H |
Thickness | 500 μm ± 15 μm | 500 μm ± 25 μm |
Wafer Orientation | On axis: <600h > 0.5° | On axis: <000h > 0.5° |
Electrical Properties | ||
Micropipe Density (MPD) | ≤1 cm⁻² | ≤15 cm⁻² |
Resistivity | ≥150 Ω·cm | ≥1.5 Ω·cm |
Geometric Tolerances | ||
Primary Flat Orientation | (0x10) ± 5.0° | (0x10) ± 5.0° |
Primary Flat Length | 52.5 mm ± 2.0 mm | 52.5 mm ± 2.0 mm |
Secondary Flat Length | 18.0 mm ± 2.0 mm | 18.0 mm ± 2.0 mm |
Secondary Flat Orientation | 90° CW from Prime flat ± 5.0° (Si face up) | 90° CW from Prime flat ± 5.0° (Si face up) |
Edge Exclusion | 3 mm | 3 mm |
LTV / TTV / Bow / Warp | ≤2.5 μm / ≤5 μm / ≤15 μm / ≤30 μm | ≤10 μm / ≤15 μm / ≤25 μm / ≤40 μm |
Surface Quality | ||
Surface Roughness (Polish Ra) | ≤1 nm | ≤1 nm |
Surface Roughness (CMP Ra) | ≤0.2 nm | ≤0.2 nm |
Edge Cracks (High-Intensity Light) | Not permitted | Cumulative length ≥10 mm, single crack ≤2 mm |
Hexagonal Plate Defects | ≤0.05% cumulative area | ≤0.1% cumulative area |
Polytype Inclusion Areas | Not permitted | ≤1% cumulative area |
Visual Carbon Inclusions | ≤0.05% cumulative area | ≤1% cumulative area |
Silicon Surface Scratches | Not permitted | ≤1 wafer diameter cumulative length |
Edge Chips | None allowed (≥0.2 mm width/depth) | ≤5 chips (each ≤1 mm) |
Silicon Surface Contamination | Not specified | Not specified |
Packaging | ||
Packaging | Multi-wafer cassette or single-wafer container | Multi-wafer cassette or |
Target Applications:
The homoepitaxial layer grown on the 4H-N type SiC substrate provides an optimized active layer for manufacturing high-performance power and RF devices. The epitaxial process allows precise control over layer thickness, doping concentration, and crystal quality.
Core Characteristics:
Customizable Electrical Parameters: The thickness (typical range 5-15 µm) and doping concentration (e.g., 1E15 - 1E18 cm⁻³) of the epitaxial layer can be customized according to device requirements, with good uniformity.
Low Defect Density: Advanced epitaxial growth techniques (such as CVD) can effectively control the density of epitaxial defects like carrot defects and triangular defects, enhancing device reliability.
Inheritance of Substrate Advantages: The epitaxial layer inherits the excellent properties of the 4H-N type SiC substrate, including wide bandgap, high breakdown electric field, and high thermal conductivity.
6-inch N-type epit axial specification | |||
Parameter | unit | Z-MOS | |
Type | Condutivity / Dopant | - | N-type / Nitrogen |
Buffer Layer | Buffer Layer Thickness | um | 1 |
Buffer Layer Thickness Tolerance | % | ±20% | |
Buffer Layer Concentration | cm-3 | 1.00E+18 | |
Buffer Layer Concentration Tolerance | % | ±20% | |
1st Epi Layer | Epi Layer Thickness | um | 11.5 |
Epi Layer Thickness Uniformity | % | ±4% | |
Epi Layers Thickness Tolerance((Spec- Max ,Min)/Spec) | % | ±5% | |
Epi Layer Concentration | cm-3 | 1E 15~ 1E 18 | |
Epi Layer Concentration Tolerance | % | 6% | |
Epi Layer Concentration Uniformity (σ /mean) | % | ≤5% | |
Epi Layer Concentration Uniformity <(max-min)/(max+min> | % | ≤ 10% | |
Epitaixal Wafer Shape | Bow | um | ≤±20 |
WARP | um | ≤30 | |
TTV | um | ≤ 10 | |
LTV | um | ≤2 | |
General Characteristics | Scratches length | mm | ≤30mm |
Edge Chips | - | NONE | |
Defects defination | ≥97% (Measured with 2*2, Killer defects inludes: Defects include Micropipe /Large pits, Carrot, Triangular | ||
Metal contamination | atoms/cm² | d f f ll i ≤5E10 atoms/cm2 (Al, Cr, Fe, Ni, Cu, Zn, Hg,Na,K, Ti, Ca &Mn) | |
Package | Packing specifications | pcs/box | multi-wafer cassette or single wafer container |
8-inch N-type epitaxial specification | |||
Parameter | unit | Z-MOS | |
Type | Condutivity / Dopant | - | N-type / Nitrogen |
Buffer layer | Buffer Layer Thickness | um | 1 |
Buffer Layer Thickness Tolerance | % | ±20% | |
Buffer Layer Concentration | cm-3 | 1.00E+18 | |
Buffer Layer Concentration Tolerance | % | ±20% | |
1st Epi Layer | Epi Layers Thickness Average | um | 8~ 12 |
Epi Layers Thickness Uniformity (σ/mean) | % | ≤2.0 | |
Epi Layers Thickness Tolerance((Spec -Max,Min)/Spec) | % | ±6 | |
Epi Layers Net Average Doping | cm-3 | 8E+15 ~2E+16 | |
Epi Layers Net Doping Uniformity (σ/mean) | % | ≤5 | |
Epi Layers Net DopingTolerance((Spec -Max, | % | ± 10.0 | |
Epitaixal Wafer Shape | Mi )/S ) Warp | um | ≤50.0 |
Bow | um | ± 30.0 | |
TTV | um | ≤ 10.0 | |
LTV | um | ≤4.0 (10mm×10mm) | |
General Characteristics | Scratches | - | Cumulative length≤ 1/2Wafer diameter |
Edge Chips | - | ≤2 chips, Each radius≤1.5mm | |
Surface Metals Contamination | atoms/cm2 | ≤5E10 atoms/cm2 (Al, Cr, Fe, Ni, Cu, Zn, Hg,Na,K, Ti, Ca &Mn) | |
Defect Inspection | % | ≥ 96.0 (2X2 Defects include Micropipe /Large pits, Carrot, Triangular defects, Downfalls, Linear/IGSF-s, BPD) | |
Surface Metals Contamination | atoms/cm2 | ≤5E10 atoms/cm2 (Al, Cr, Fe, Ni, Cu, Zn, Hg,Na,K, Ti, Ca &Mn) | |
Package | Packing specifications | - | multi-wafer cassette or single wafer container |
Target Applications:
It is the core material for manufacturing high-voltage power devices (such as MOSFETs, IGBTs, Schottky diodes), widely used in electric vehicles, renewable energy power generation (photovoltaic inverters), industrial motor drives, and aerospace fields.
ZMSH plays a key role in the silicon carbide (SiC) substrate industry, focusing on the independent R&D and large-scale production of critical materials. Mastering core technologies spanning the entire process from crystal growth, slicing, to polishing, ZMSH possesses the industrial chain advantage of an integrated manufacturing and trading model, enabling flexible customized processing services for customers.
ZMSH can provide SiC substrates in various sizes from 2-inch to 12-inch diameters. The product types cover multiple crystal structures including 4H-N type, 6H-P type, 4H-HPSI (High-Purity Semi-Insulating) type, 4H-P type, and 3C-N type, meeting the specific requirements of different application scenarios.
Q1: What are the three main types of SiC substrates and their primary applications?
A1: The three primary types are 4H-N type (conductive) for power devices like MOSFETs and EVs, 4H-HPSI (high-purity semi-insulating) for high-frequency RF devices such as 5G base station amplifiers, and 6H type which is also used in certain high-power and high-temperature applications.
Q2: What is the fundamental difference between 4H-N type and semi-insulating SiC substrates?
A2: The key difference lies in their electrical resistivity; 4H-N type is conductive with low resistivity (e.g., 0.01-100 Ω·cm) for current flow in power electronics, while semi-insulating types (HPSI) exhibit extremely high resistivity (≥ 10⁹ Ω·cm) to minimize signal loss in radio frequency applications.
Q3: What is the key advantage of HPSI SiC wafers in high-frequency applications like 5G base stations?
A3: HPSI SiC wafers provide extremely high resistivity (>10⁹ Ω·cm) and low signal loss, making them ideal substrates for GaN-based RF power amplifiers in 5G infrastructure and satellite communications.
Tags: #SiC wafer, #SiC Epitaxial wafer, #Silicon Carbide Substrate, #4H-N, #HPSI, #6H-N, #6H-P, #3C-N, #MOS or SBD, #Customized, #2inch/3inch/4inch/6inch/8inch/12inch
Company Details
Business Type:
Manufacturer,Agent,Importer,Exporter,Trading Company
Year Established:
2013
Total Annual:
1000000-1500000
Ecer Certification:
Verified Supplier
SHANGHAI FAMOUS TRADE CO.,LTD. locates in the city of Shanghai, Which is the best city of China, and our factory is founded in Wuxi city in 2014. We specialize in processing a varity of materials into wafers, substrates and custiomized optical glass parts.components widely used in electronics, op... SHANGHAI FAMOUS TRADE CO.,LTD. locates in the city of Shanghai, Which is the best city of China, and our factory is founded in Wuxi city in 2014. We specialize in processing a varity of materials into wafers, substrates and custiomized optical glass parts.components widely used in electronics, op...
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